Prof. Hiroshi Iwai
Prof. Hiroshi Iwai
Tokyo Institute of Technology, Japan
Title: CMOS miniaturization and gate-oxide thinning toward its limit
CMOS LSIs have been (large scale integrated circuits)the key component of modern intelligent society, and the tremendous progress of CMOS LSIs in the past 50 years has been accomplishedby the miniaturization of its components such as MOSFETs. The miniaturization increases the number of components and reduces their capacitance, resulting in decrease in the cost and power consumption per function and increase in the performance.In 1970 when the first generation of LSI was produced, the feature size of the MOSFETs such as the gate length was 10 um. After half a century from 1970, so-called ‘10 nm technology’ has been introduced into production, although the gate length is around 25 nm and much larger than 10 nm because of the technology difficulty. In the course of the miniaturization, the gate oxide thinning has always been a critical issue because the property of the interface between Si substrate and the gate oxide determines the performance and reliability of MOSFETs. Since 1970 when the gate oxide thickness was 100 nm, the thickness continued to decrease down to sub-1.0 nm by the development of new techniques including the introduction of new materials. However, the gate oxide thinning is reaching its limits because of increase of the oxide leakage current, mobility and long term reliability degradation. What is the limit of the gate oxide thinning? It is expected to about 0.4 nm when the gate length becomes about 5 nm. In this paper, past, present, and future of the gate oxide technologydevelopment will be described in detail.
Hiroshi Iwai received the B.E. and Ph.D. degrees in electrical engineering from the University of Tokyo and worked in the research and development of integrated circuit technology for more than 25 years in Toshiba. He is now a professor of Frontier Collaborative Research Center and Dept. of Electronics and Applied Physics, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama, Japan. Since joining Toshiba, he has developed several generations of high density static RAM's, dynamic RAM's and logic LSI's including CMOS, bipolar, and Bi-CMOS devices. He has also been engaged in research on device physics, process technologies, and T-CAD related to small-geometry MOSFETs and high speed bipolar transistors. He has authored and coauthored more than 600 journal and conference papers. He has served on many committees of conferences and editors of journals, as well as a member of many evaluation committee of public organizations. For example, the President of the IEEE EDS, an elected member of the IEEE EDS AdCom, an editor of IEEE EDS Newsletter, a guest editor of IEEE Trans. on Electron Devices, and an editor of the Proceedings of ECS Symp. on ULSI Process Integration. He is now the IEEE Division 1 Director for 2010-11 and ECS Individual Membership Committee member for 2009-2011. He serves as a visiting professor for many Chinese and Indian universities. His awards include Local Commendation for Invention from Japan Institute of Invention and Innovation (1990, 2005), Grand Prize of Nikkei BP Technology Awards (1994), IEEE EDS Paul Rappaport Award (1994), IEICE ES Electronics Award (1998), IEEE EDS J.J.Ebers Award (2001), and JSAP Award for the best paper (2002), IEEE BCTM Award (2007), Yamazaki-Teiichi Prize (2007), IEEE 2008 EDS Distinguished Service Award (2008), The Commendation for Science and Technology by the Minister of Education, Culture, Science and Technology, Prizes for Science and Technology, Development Category Award (2009). His current research interests are Nano CMOS and Emerging Technologies: High–k gate insulator, Si Nanowire MOSFETs, plasma doping for ultra-shallow junctions, Ni salicide, RF CMOS modeling, and Ge transisters. Dr. Iwai is, a fellow of IEEE, a member of Electrochemical Society, a fellow of the Japan Society Applied Physics, and a fellow of the Institute of Electronics, Information and Communication Engineers of Japan.