• Published Papers
  • Open Access
  • A spatiotemporal signal processing technique for wafer-scale IC thermomechanical stress monitoring by an infrared camera
  • DOI: 10.4236/jbm.2013.12001   PP.1 - 5, Pub. Date: November 8 , 2013
  • Author(s)
  • Michel Saydé, Ahmed Lakhssassi, Emmanuel Kengne, Roman Palenichka
  • ABSTRACT
  • In this paper, we describe a new silicon-die thermal monitoring approach using spatiotemporal signal processing technique for Wafer-Scale IC thermome- chanical stress monitoring. It is proposed in the context of a wafer-scale-based (WaferICTM) rapid prototyping platform for electronic systems. This technique will be embedded into the structure of the WaferIC, and will be used as a preventive measure to protect the wafer from possible damages that can be caused by excessive thermomechanical stress. The paper also presents spatial and spatiotemporal algorithms and the experimental results from an IR images collection campaign conducted using an IR camera.
  • KEYWORDS
  • Thermal Monitoring; Ring Oscillator (RO); Spatial; Spatiotemporal; Thermo-Mechanical Stress; Temperature Sensor; Thermal Analysis; WaferIC; Wafer-Scale System
  • References
  • [1] Norman, R., Valorge, O., Blaquiere, Y., Lepercq, E., Basile-Bellavance, Y., El-Alaoui, Y., Prytula, R. and Savaria, Y. (2008) An active reconfigurable circuit board. 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, 351-354.

    [2] Norman, R., Lepercq, E., Blaquiere, Y., Valorge, O., Basile-Bellavance, Y., Prytula, R. and Savaria, Y. (2008) An interconnection network for a novel reconfigurable circuit board. 2008 Joint 6th International IEEE North-east Workshop on Circuits and Systems and TAISA Conference, 129-132.

    [3] Lepercq, E., Valorge, O., Basile-Bellavance, Y., Laflamme-Mayer, N., Blaquiere, Y. and Savaria, Y. (2009) An interconnection network for a novel reconfigurable circuit board. 2nd Microsystems and Nanoelectronics Research Conference, 53-56.

    [4] Sergent, J. and Krum, A. (1998) Thermal management handbook for electronic assemblies. McGraw-Hill, New York, Chapter 1, 1.1.

    [5] Tze-chiang, C. (2006) Where CMOS is going: Trendy hype vs. real technology. IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 1-18.

    [6] Jaewon O. and Pedram, M. (2001) Gated clock routing for low-power microprocessor design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20, 715-722. http://dx.doi.org/10.1109/43.924825

    [7] Stok, L., Puri, R., Bhattacharya, S., Cohn, J., Sylvester, D., Srivastava, A. and Kulkarni, S. (2007) Pushing ASIC performance in a power envelope. Closing the Power Gap between ASIC & Custom, Springer US, 323-356.

    [8] Srivastava, A., Sylvester, D. and Blaauw, D. (2004) Concurrent sizing, Vdd and Vth assignment for low-power design. Proceedings of Design, Automation and Test in Europe Conference and Exhibition, 1, 718- 719.

    [9] Kao, J., Chandrakasan, A. and Antoniadis, D. (1997) Transistor sizing issues and tool for multi-threshold CMOS technology. Proceedings of the 34th annual Design Automation Conference, Anaheim, 409-414. http://dx.doi.org/10.1109/DAC.1997.597182

    [10] Changbo L. and Lei, H. (2004) Distributed sleep transistor network for power reduction. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12, 937- 946.

    [11] Gronowski, P.E., Bowhill, W.J., Preston, R.P., Gowan, M.K. and Allmon, R.L. (1998) High-performance microprocessor design. IEEE Journal of Solid-State Circuits, 33, 676-686. http://dx.doi.org/10.1109/4.668981

    [12] Yeh, L.T. (1995) Review of Heat Transfer Technologies in Electronic Equipment. Journal of Electronic Packaging, 117, 333-339. http://dx.doi.org/10.1115/1.2792113

    [13] Sayde, M., Berriah, O., Lakhssassi, A., Bougataya, M., Kengne, E. and Talbi, L. (2001) Silicon-die thermal monitoring using embedded sensor cells unit. 2011 IEEE 9th International on New Circuits and Systems Conference (NEWCAS), 153-156.

    [14] Rafael P.H.D., Gonzalez C. and Woods, R.E. (2008) Digital image processing. 3rd Edition, Prentice Hall.


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